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Technological innovation From PCIe 4.0 to PCIe 5.0

post @ July 27, 2022 12:41 Ellie Ross

Technological innovation and user needs are superimposed to accelerate the evolution of PCIe from 4.0 to 5.0

Based on the early evolution of PCIe and the key development of the applications behind it (big data, mobile internet, artificial intelligence), the demand for data traffic and technical capabilities promote each other, and the capabilities of computing, networking and storage have grown exponentially, creating a prosperous ecological environment. By this article, we will look forward to the future evolution of PCIe - what we will see will not be just a doubling of bandwidth, but more novel ideas and grander visions.

From PCIe 4.0 to PCIe 5.0

What happened in the application area between 2017 and 2019 is that the new workloads, primarily AI/ML and cloud-based, shifted the focus of virtualization from one server running multiple processes to multiple processors connected to handle a single, massive workload.

01 Artificial intelligence and machine learning applications

With the deployment of next-generation 5G cellular networks around the world, the related technical theory has been partially successfully translated into productivity after several years of exploration, leading to artificial intelligence becoming ubiquitous. With advances in machine learning and deep learning, AI workloads generate, move, and process massive amounts of data at real-time speeds.

02 The continuous development of cloud computing

Enterprise workloads have migrated to the cloud. In 2017, 45% of workloads were cloud-based, and more than 60% of workloads migrated to the cloud in 2019. As time goes by, it is certain that more workloads will be cloud-based. Data centers are ramping up hyperscale computing and networking to meet the demands of cloud-based workloads.

03 Virtual reality/augmented reality (VR/AR), self-driving cars are popular research fields

The I/O infrastructure requirements of these applications can be largely summed up as:
Greater I/O interconnection bandwidth to accommodate the collaboration of more accelerators and TPUs;
Faster network protocols to support economies of scale;
Faster and wider channels on the data link, less latency.
The shortcomings of PCIe 4.0 have actually been revealed. For example, NVIDIA innovated NVSwitch in 2018, using its private NVlink protocol to interconnect multiple GPUs. The first generation of NVSwitch is 300GB/s, while the bandwidth of PCIe 4.0 x16 in 2017 is 64GB/s.


Image source: NVIDIA official website

In terms of storage, NMVe continues to upgrade steadily. NVMe-oF adds TCP Transport binding to RDMA binding. This new routing capability significantly enhances the flexibility of hybrid cloud and multi-cloud .

Combining application requirements with the development of compute units, network units and storage units, the vision of the PCIe 5.0 definition is: "a game-changer for data center/cloud computing, and built-in support for alternative protocols in the future." PCIe 5.0 features a modified training Sequence (TS1 & TS2), a new field with ID for future alternative protocols and enhanced precoding. This marks the opening of the PCIe standard, allowing future protocols to use some of the proven PCIe firmware and software stacks, and to expand the scope and capabilities of PCIe. In short, the physical layer of future PCIe can accept connections from different protocols. PCIe 5.0 provides high-bandwidth and low-latency connectivity for next-generation applications in artificial intelligence/machine learning (AI/ML), data center, edge, 5G infrastructure and graphics.

The PCIe6 specification was released in January 2022, and its vision is "heterogeneous computing applications, such as artificial intelligence, machine learning and deep learning." Technically, PCIe 6.0 will be updated from the coding type, number of bits treated per cycle and packet type that have not changed in the past generations. PCIe 6.0 will be a more comprehensive upgrade.

The relatively simple reason is that Intel has accelerated the pace of processor development in order to improve its competitiveness, including the breakthrough of manufacturing process bottlenecks (the relatively slow progress of manufacturing process leads to the delay in the launch of new cores, which is also one of the reasons why Intel platform is late in the era of PCIe 4.0).

The relatively deep-seated reason is that PCIe 5.0 is an important watershed in the development of PCIe, which is not only the end of one era, but also the beginning of another era.

The so-called end means that the frequency of PCIe has been nearly doubled in previous generations. In PCIe 5.0, the cost of maintaining signal integrity and reducing loss has reached a high point (there will be further analysis in future articles). To control the cost for signal quality assurance, we need to change our thinking.

An available approach is changing the modulation method (such as for PCIe 6.0 changing from NRZ to PAM4 pulse modulation); or reducing the number of channels used by a device - since the bandwidth of PCIe 5.0 x4 is equivalent to PCIe 3.0x16, some future devices can use fewer channels. For example, the 25/40Gb network card can use x4 channels, and the graphics card can use x8 or even x4 channels, which is conducive to reducing the complexity of the controller and the size of the connector. It can be expected that x4 channel will be a standard interface form for many devices including SSD. The performance/cost positioning of most devices may no longer be distinguished by x4, x8, or x16, but by PCIe versions (multiple versions coexist at the same time, for example, PCIe4.0 x4 devices are cost-effective, while PCIe 5.0/6.0 x4 devices are of medium and high performance).

Now that a new era has begun , CXL (Compute Express Link) should be mentioned. CXL is an open interconnection protocol launched by Intel in 2019, in an attempt to achieve high-speed and efficient interconnection among CPU, GPU, FPGA and other accelerators so that the requirements can be met for high-performance heterogeneous computing. The point is: the interface specification of the CXL standard is compatible with PCIe 5.0. Therefore, investing in PCIe 5.0 as soon as possible is equivalent to building a road for the popularization of CXL. In addition, CXL can also change the traditional form of accelerator and memory (internal card), making it a more maintainable module...Well, smart readers may have already thought that front-end, hot-plugging is feasible, Isn't this the EDSFF we mentioned in the previous article?

That's right. We have explained that EDSFF is not only used for SSD, but also for memory devices, accelerator cards, etc. In terms of appearance alone, EDSFF is one of the few redesigned structures in the x86 world that emphasizes compatibility and inheritance in recent decades, without the historical burden of inheriting any modules (for example, U.2 has inherited the form of the 2.5-inch hard disk). It is completely optimized for the size of 1U and 2U chassis, and its deployment density and heat dissipation efficiency far exceed the old 2.5 and 3.5-inch modules. It can be said that the combination of PCIe 5.0/6.0, CXL and EDSFF is enough to revolutionize the deployment efficiency of racks. This is the evolution from "can do it" (with enough bandwidth) to "do it well": first meet basic needs, and then optimize in a targeted manner to trigger evolution.

Conclusion:

Looking back at the development of the bus, the upgrade of each generation of PCIe depends on "whether there is a need" and "whether it is technically ready". That the upgrade cycle was long was because the infrastructure bottleneck faced by the applications at that time was not on the system bus. That the upgrade cycle was short was because the bus at that time could not meet the needs of the rapidly developing applications. Demand drives technological development, and technology opens up new demand— this is a pattern that existed before and will continue to be there in the future.

post @ July 27, 2022 12:41 Ellie Ross views(66) comment(0)
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